High performance computers generally have an interconnect backplane. The interconnect backplane provides an interconnection path between various components of the computer. Typically, about 5-6 components are interconnected. The components may be microprocessors, memory or other computer associated circuitry.
FIG. 1 shows a computer interconnect backplane 10. The interconnect backplane 10 is typically a printed circuit board. The interconnect backplane 10 has a bus 12 which interconnects components 14, 15, 16, 17, 18, 19 of the computer. Each of the components can include integrated circuits (ICs) such as an IC 20 attached to component 14. Typically, a matched impedance 22 is attached to both ends of the bus 12.
The speed of the microprocessors and memory connected to the interconnection backplane is constantly increasing. As the speed of the circuitry increases, parasitic capacitance and impedance mismatches on the interconnection bus 12 begin to affect the integrity of the signals traveling on the bus from one component to another. As a result, the technology used to implement the interconnection backplane must evolve as the components connected to the backplane operate at faster speeds.
Presently, computer interconnection backplanes are implemented as suggested by the circuit schematic shown in FIG. 2. The bus is implemented with bus transmission lines 24, 25, 26, 27, 28 that interconnect the components attached to the bus at a series of node interconnect points 0, 1, 2, 3, 4, 5. The bus transmission lines can be implemented with microstrip or stripline, and have a characteristic impedance of Z.sub.o. Termination impedance loads 36, 37 are located at the two end nodes 0, 5. The components 30, 31, 32, 33, 34, 35 connected to the nodes are devices that are either in a driver mode or in a listener mode. Only a single one of the components 30, 31, 32, 33, 34, 35 may be in driver mode at a time. If a component is in driver mode then that component determines the voltage level of the interconnection bus. The driver component can be in one of two states. The driver component sets the voltage level of the bus to one of two voltage levels in which a voltage level corresponds to each state. If a component is in listener mode then that component is receiving the voltage level of the bus. The components 30, 31, 32, 33, 34, 35 in FIG. 2 are represented by input/output (I/O) devices. A component 32 is the driver device and has a low output impedance of typically less than 10 ohms. All of the other components (I/Os) 30, 31, 33, 34, 35 are depicted as listener devices and have high input impedances.
In operation, the interconnection bus operates as follows. When the driver component 32 transitions from one of two states to the other, a rising or falling edge propagates down the bus transmission lines 24, 25, 26, 27, 28 as the voltage level on the bus switches from one level to another. Each listener component 30, 31, 33, 34, 35 receives the new voltage level corresponding to the new state of the driver component as the rising or falling edge reaches the listener component. The rising or falling edge propagates to the end of the bus and is terminated because of the presence of the termination impedance loads 36, 37. The termination impedance loads 36, 37 are matched to the characteristic impedance of the bus transmission lines so that the rising or falling edges are not reflected upon reaching the termination impedance loads 36, 37.
This operation is illustrated through transient simulation of the circuit. FIG. 3 shows the results of the simulation in which Z.sub.o is 50 ohms, the driver has an output impedance of 10 ohms and an open circuit output voltage of 1 volt, each bus transmission line 24, 25, 26, 27, 28 is 300 picoseconds long, and the edge risetime is 100 picoseconds. Traces 3A, 3B and 3C show time lines of the voltage levels received by the listener components when the driver component is attached to nodes 0, 1 and 2.
Trace 3A of FIG. 3 shows the voltage level at each of the nodes 1, 2, 3, 4, 5 when the first component 30 is the driver component and transitions from a low voltage level (about 0 Volts) to a high voltage level (about 0.8 Volts). The voltage levels of the nodes 1, 2, 3, 4, 5 transition from the low voltage to the high voltage as the rising edge of the driver transition reaches each node. Trace 3B of FIG. 3 shows the voltage level at each of the nodes 0, 2, 3, 4, 5 when the second component 31 is the driver component. The voltage levels of the nodes 0, 2, 3, 4, 5 transition from the low voltage to the high voltage as the rising edge of the driver transition reaches each node. Trace 3C of FIG. 3 shows the voltage level at each of the nodes 0, 1, 3, 4, 5 when the third component 32 is the driver component. The voltage levels of the nodes 0, 1, 3, 4, 5 transition from the low voltage to the high voltage as the rising edge of the driver transition reaches each node.
The driver component changes state producing a rising or falling edge. The edge propagates down both directions of the bus away from the driving component and each listener component receives the transition in states. The edges propagate to each end of the bus and terminate with no reflections,
Difficulties arise when the listener components connected to the receiving nodes do not have a high input impedance. The listener components can have substantial parasitic capacitance due to the fact that the listener components are not connected directly to the nodes on the bus. Generally, the components are connected to the bus through connectors, IC sockets, printed circuit boards and other electrical connection devices.
Typically, the components are connected to the nodes of the bus through conductive component connection transmission line sections. The component connection transmission line sections may have a characteristic impedance that is the same as the characteristic impedance of the bus transmission lines. Therefore, impedance mismatches can occur at each node where the component connection transmission line sections make electrical contact with the bus transmission line sections. As the frequency of the transitions from the driver component increases the risetime of transition edges decreases and impedance mismatches have a greater effect on the integrity of the voltage transitions received by the listener components. Component connection transmission line sections that are tolerable with transitions of 1 nanosecond may be intolerable in faster systems. The component connection transmission line sections become "visible" when the electrical length of the component connection transmission line section is on the order of the risetime of the transition edge.
FIG. 4 is a circuit schematic that represents a typical backplane bus with component connection transmission line sections 41, 42, 43, 44 connecting components 31, 32, 33, 34 to the bus at nodes 51, 52, 53, 54, and bus transmission lines 24, 28 connecting components 30, 35 to the bus at nodes 0 and 5. The arrows on FIG. 4 depict where the impedance mismatches within the backplane interconnection bus are located. At each impedance mismatch, a reflection will occur if a high speed rising or falling voltage transitional edge propagates into the impedance mismatch. The mismatches are located so that a single edge may reflect back and forth between impedance mismatches causing tinging. The ringing will cause the interconnection bus to take a longer period of time to reach a static voltage level.
FIG. 5 shows the results of a transient simulation of the circuit schematic of FIG. 4 in which Z.sub.o is 50 ohms, the driver has an output impedance of 10 ohms and an open circuit output voltage of 1 volt, each bus transmission line 24, 25, 26, 27, 28 is 300 picoseconds long, each component connection transmission line sections 41, 42, 43, 44 is 200 picoseconds long, and the edge risetime is 100 picoseconds. Traces 5A, 5B and 5C show time lines of the voltage levels received at nodes 54 and 5 when the driver component is components 30, 31, 32.
Trace 5A shows the voltage levels received at nodes 54 and 5 when the driver component is component 30. The two waveforms depict the delay as the voltage transition of the driver travels down the interconnection bus. The two waveforms also show the distortion of the voltage transition due to the additive and subtractive components of the reflected components of the voltage transition as the transition encounters impedance mismatches on the interconnection bus. Trace 5B shows the voltage levels received at nodes 54 and 5 when the driver component is component 31. Trace 5C shows the voltage levels received at nodes 54 and 5 when the driver component is component 32.
Traces 5A, 5B and 5C show that the voltage levels at all nodes and connection points on the interconnection bus take longer to reach a static state when the driver component operates with a rise or fall time equal to or less than the electrical length of the bus transmission line sections 24, 25, 26, 27, 28 and the component connection transmission line sections 41, 42, 43, 44. The distortion to voltage transitions on the interconnection bus due to the impedance mismatches on the interconnection bus reduces the rate at which, the voltage transitions can occur since each voltage transition must be substantially settled at a receiving node before subsequent transitions arrive in order to avoid bit errors. The rate limitation reduces the frequency at which signals on the interconnection bus can be usefully coupled between components connected to the interconnection bus.
The operating frequencies of the components connected to computer interconnection backplanes are constantly increasing. Therefore, new configurations and new methods of fabricating computer interconnection backplanes must be developed.